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CXA2074Q/S
US Audio Multiplexing Decoder
Description The CXA2074Q/S is an IC designed as a decoder for the Zenith TV Multi-channel System and also corresponds with I2C BUS. Functions include stereo demodulation, SAP (Separate Audio Program) demodulation, dbx noise reduction and sound processor. Various kinds of filters are built in while adjustment, mode control and sound processor control are all executed through I2C BUS. Features * Audio multiplexing decoder, dbx noise reduction decoder and sound processor are all included in a single chip. Almost any sort of signal processing is possible through this IC. * All adjustments are possible through I2C BUS to allow for automatic adjustment. * Various built-in filter circuits greatly reduce external parts. * There are three systems for inputs and two systems for outputs, and each mode control is possible. Standard I/O Level [( ) is the pin No. for the CXA2074S.] * Input level COMPIN (Pin 17) 245mVrms AUX1-L/R (Pins 36 and 35) 490mVrms AUX2-L/R (Pins 38 and 37) 490mVrms * Output level LPOUT-L/R (Pins 40 and 39) 490mVrms LSOUT-L/R (Pins 8 and 7) 490mVrms CXA2074Q 48 pin QFP (Plastic) CXA2074S 42 pin SDIP (Plastic)
Absolute Maximum Ratings (Ta = 25C) * Supply voltage VCC 11 V * Operating temperature Topr -20 to +75 C * Storage temperature Tstg -65 to +150 C * Allowable power dissipation PD 0.6 (48 pin QFP) W 2.2 (42 pin SDIP) W Range of Operating Supply Voltage 9 0.5
V
Applications TV, VCR and other decoding systems for US audio multiplexing TV broadcasting Structure Bipolar silicon monolithic IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E96843A6Y-PS
CXA2074Q/S
Pin Configuration (Top View) CXA2074Q
VCAWGT AUX1-R VCAIN VEWGT AUX1-L VCATC VEOUT SAPIN
24 SAPOUT 23 NOISETC 22 STIN 21 SUBOUT 20 NC 19 VCC 18 SAPTC 17 GND 16 IREF 15 VGR 14 COMPIN 13 PLINT 1 2 3 4 5 6 7 8 9 10 11 12
NC
NC
VETC
36 35 34 AUX2-R 37 AUX2-L 38 LPOUT-R 39 LPOUT-L 40 LPIN-R 41 LPIN-L 42 NC 43 BASSR1 44 BASSR2 45 BASSL1 46 BASSL2 47 TRER 48
33 32
31 30
29 28 27 26 25
SDA
NC
LSOUT-R
SCL
MAININ
NC
LSOUT-L
MAINOUT
PCINT1
DGND
VE
CXA2074S
VCAWGT NOISETC LPOUT-R LPOUT-L SAPOUT SUBOUT
23 20
AUX2-R
AUX2-L
AUX1-R
VEOUT
LPIN-R
VCAIN
VEWGT
AUX1-L
LPIN-L
VCATC
PCINT2
SAPIN
TREL
VETC
STIN
42
41
40
39
38
37
36
35
34
33
32
31
VE
30
29
28
27
26
25
24
22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
21
LSOUT-L
BASSR2
LSOUT-R
BASSL1
DGND
TRER
SDA
MAINOUT
PCINT1
PCINT2
TREL
MAININ
COMPIN
BASSL2
PLINT
BASSR1
-2-
SAPTC
SCL
VGR
IREF
GND
VCC
Block Diagram
PCINT1
MAINOUT
PCINT2
PLINT
SUBOUT
MAININ
11 21 9 8
12 36
13 35
STLPF
LFLT MATRIX TVSW FLT LPF VCA
VCO
1/4
1/2
FEXT1
"FILTER"
AUX1-L
AUX1-R
CXA2074Q
38
AUX2-L 37 AUX2-R
FEXT2 40 LPOUT-L 39 LPOUT-R 42 LPIN-L
"STEREO" DeEm NRSW/FOMO/SAPC (+6dB) LPF WIDEBAND
TVSW/EXT/M1
COMPIN 14
VCA
LPF
PSW
ATT LOGIC
STIND
PASSSW 41 LPIN-R
VCC 19
VOL-R VOL-L
VOL-R
BPF DeEm "NOISE" VE
SAPVCO
LPF VCA
VOL-L
BASS
BASS
BASS
TREB
"PONRES" 5 4 22 24 25 26 27 28 30 31 33 32
15
M2 TREBLE
SW
16
6
3
SCL
VGR
IREF
SDA
STIN
VE
SAPIN
VETC
DGND
VCAIN
SAPOUT
VEWGT
VEOUT
VCATC
VCAWGT
LSOUT-L
LSOUT-R
TREB
-3-
"SAP" HPF RMSDET SPECTRAL LPF LPF AMP (+4dB)
GND 17
46
BASSL1 47 BASSL2 44 BASSR1 45 BASSR2 1 RMSDET TREL
NOISETC 23
NOISE DET
SAPTC 18
SAPIND
VCO FILTER
IREF
I2C BUS I/F
48
TRER
2
CXA2074Q/S
CXA2074S
AUX1-L
36 35
PCINT1
MAINOUT
PCINT2
PLINT
SUBOUT
14 16
15
23 12
13
STLPF
LFLT MATRIX TVSW FLT LPF VCA
VCO
1/4
1/2 38 AUX2-L 37 AUX2-R FEXT2 40 LPOUT-L 39 LPOUT-R 42 LPIN-L
"STEREO" DeEm LPF NRSW/FOMO/SAPC (+6dB) WIDEBAND
TVSW/EXT/M1
COMPIN 17
VCA
LPF
FEXT1
"FILTER"
MAININ
ATT LOGIC
STIND
PSW
PASSSW 41 LPIN-R
VCC 22
VOL-L
VOL-L
BPF DeEm "NOISE" VE
LPF VCA
VOL-R
SAPVCO
VOL-R
BASS
BASS
BASS
TREB
"PONRES" 10 24 9 26 27 28 29 30 31 32 34 33
18
19
M2 TREBLE
SW
11
8
SCL
VGR
IREF
SDA
STIN
VE
DGND
SAPIN
VETC
VCAIN
VEWGT
VEOUT
VCATC
SAPOUT
VCAWGT
LSOUT-L
LSOUT-R
TREB
-4-
"SAP" HPF RMSDET SPECTRAL AMP (+4dB) LPF LPF
GND 20
AUX1-R
3 4 1 2 6 RMSDET
BASSL1 BASSL2 BASSR1 BASSR2 TREL
NOISETC 25
NOISE DET
SAPTC 21
SAPIND
VCO FILTER
IREF
I2C BUS I/F
5
TRER
7
CXA2074Q/S
CXA2074Q/S
Pin Description Pin No.
QFP SDIP
Symbol
Pin voltage
Equivalent circuit
Description BASS filter pin. (Right channel) (Connect a 47nF capacitor between Pins 1 and 2 (44 and 45).) The cutoff frequency is determined by the built-in resistor and the external capacitance. BASS filter pin. (Left channel) (Connect a 47nF capacitor between Pins 3 and 4 (46 and 47).) The cutoff frequency is determined by the built-in resistor and the external capacitance.
44
1
BASSR1
4.0V
VCC 3k
(45) 2
190 4.2k 3.4k 2.7k 2.2k 190
45
2
BASSR2
4.0V
(47) 4
46
3
BASSL1
4.0V
1.8k 1.4k 1.2k 4.9k
VCC
1 (44) 3 (46)
47
4
BASSL2
4.0V
4V
VCC 3k
48
5
TRER
4.0V
580 4.2k 3.4k 2.7k 2.2k 1.8k 1.4k VCC 1.2k 4.9k (48) 5 (1) 6 580
TREBLE filter pin. (Right channel) (Connect a 6.8nF capacitor between this pin and GND.)
1
6
TREL
4.0V
TREBLE filter pin. (Left channel) (Connect a 6.8nF capacitor between this pin and GND.)
VCC 3k
2
7
LSOUT-R 4.0V
VCC 580 (2) 7 (3) 8 580
LSOUT right channel output pin.
3
8
LSOUT-L
4.0V
LSOUT left channel output pin.
-5-
CXA2074Q/S
Pin No.
QFP SDIP
Symbol
Pin voltage
Equivalent circuit
VCC 7.5k 35 2.1V x2 4k x5 7.5k 4.5k 3k
Description
4
9
SDA
--
Serial data I/O pin. VIH > 0V VIL < 1.5V
9 (4)
VCC 7.5k 35 2.1V 4k
5
10
SCL
--
10.5k
x4
3k
Serial clock input pin. VIH > 3.0V VIL < 1.5V
10 (5)
6
11
DGND
--
11 (6)
VCC 10k
Digital block GND.
8
12
MAININ
VCC
4.0V
147 12 (8) 53k 4V
Input the (L + R) signal from MAINOUT (Pin 13 (9)).
VCC 15k x4 VCC
9
13
MAINOUT 4.0V
13 (9)
147
(L + R) signal output pin.
200
1k
-6-
CXA2074Q/S
Pin No.
QFP SDIP
Symbol
Pin voltage
Equivalent circuit
Description
VCC 147 14 (11) 30k
11
14
PCINT1
4.0V
22k
Stereo block PLL loop filter integrating pin.
VCC 147 15
12
15
PCINT2
4.0V
(12) 2k
10k
10k
x2 4k
VCC 20k 20k
13
16
PLINT
5.1V
20k 20k
147 16 (13)
Pilot cancel circuit loop filter integrating pin. (Connect a 1F capacitor between this pin and GND.)
26
20k 50
10k
VCC 50k 147 17 (14)
14
17
COMPIN
4.0V
22k 3V 4k 4k 4k
20k 3k
Audio multiplexing signal input pin.
16k
24k
-7-
CXA2074Q/S
Pin No.
QFP SDIP
Symbol
Pin voltage
Equivalent circuit
Description
3k
147
15
18
VGR
1.3V
11k
9.7k
19.4k x4 18
VCC 11k 11k
Band gap reference output pin. (Connect a 10F capacitor between this pin and GND.)
2.06k
(15)
VCC 40k 40k 30k 30k 15k x2 30k
VCC
16
19
IREF
1.3V
30p 1.8k 19 147 6.3k (16)
Set the filter and VCO reference current. The reference current is adjusted with the BUS DATA based on the current which flows to this pin. (Connect a 62k (1%) resistor between this pin and GND.)
16k
17
20
GND
--
VCC 8k
20 (17)
Analog block GND.
10k 3k 1k VCC 4k 50 21 (18)
18
21
SAPTC
4.5V
Set the time constant for the SAP carrier detection circuit. (Connect a 4.7F capacitor between this pin and GND.)
19
22
VCC
--
22 (19)
Supply voltage pin.
-8-
CXA2074Q/S
Pin No.
QFP SDIP
Symbol
Pin voltage
Equivalent circuit
Vcc 2k 2k 10P 4k
Description
580
21
23
SUBOUT 4.0V
2k 2k 14.4k 580 147
23 (21)
(L - R) signal output pin.
2k
4k
1k
VCC 23k
22
24
STIN
23k
4.0V
11.7k 147 24 147 27 18k 4V 20k 4V
Vcc 8k 3.3k
Input the (L - R) signal from SUBOUT (Pin 23 (21)).
25
27
SAPIN
4.0V
(22)
18k
(25)
Input the (SAP) signal from SAPOUT (Pin 26 (24)).
10k 1k 2k 4k 4V 3k Vcc 3k
23
25
NOISETC 3.0V
x2
Set the time constant for the noise detection circuit. (Connect a 4.7F capacitor between this pin and GND.)
200k 25 (23)
Vcc 5P
580
24
26
SAPOUT 4.0V
580
10k 26 147 (24)
SAP FM detector output pin.
24k 10
4k 50
-9-
CXA2074Q/S
Pin No.
QFP SDIP
Symbol
Pin voltage
Equivalent circuit
VCC 7.5k
Description
26
28
VE
147
4.0V
28 (26)
Variable de-emphasis integrating pin. (Connect a 2700pF capacitor and a 3.3k resistor in series between this pin and GND.)
Vcc
580
2.9V 4V 36k
27
29
VEWGT 4.0V
29 (27)
147 580
Weight the variable de-emphasis control effective value detection circuit. (Connect a 0.047F capacitor and a 3k resistor in series between this pin and GND.)
8k
30k 8
4k 50
Vcc
28
30
VETC
1.7V
x4
x4
30 (28)
4k 50
20k 7.5
Determine the restoration time constant of the variable de-emphasis control effective value detection circuit. (The specified restoration time constant can be obtained by connecting a 3.3F capacitor between this pin and GND.)
Vcc 5P 580
30
31
VEOUT
4.0V
31 (30) 580 10k
Variable de-emphasis output pin. (Connect a 4.7F non-polar capacitor between Pins 31 (30) and 32 (31).)
- 10 -
CXA2074Q/S
Pin No.
QFP SDIP
Symbol
Pin voltage
Equivalent circuit
VCC
Description
47k 20k
47k
31
32
VCAIN
4.0V
VCC
32 (31)
VCA input pin. Input the variable de-emphasis output signal from Pin 31 (30) via a coupling capacitor.
VCC
x4
32
33
VCATC
1.7V
x4
33 (32)
50
4k
7.5
20k
Determine the restoration time constant of the VCA control effective value detection circuit. (The specified restoration time constant can be obtained by connecting a 10F capacitor between this pin and GND.)
VCC 40k 40k 3p
580
33
34
VCAWGT 4.0V
34 2.9V 36k 580 147 (33)
Weight the VCA control effective value detection circuit. (Connect a 1F capacitor and a 3.9k resistor in series between this pin and GND.)
50
4k 8
30k
8k
35
35
AUX1-R 4.0V
VCC 10k
Right channel external input 1 pin. Left channel external input 1 pin. Right channel external input 2 pin. Left channel external input 2 pin.
36
36
AUX1-L
4.0V
147 35 27.5k 36 37 47k 38 4V
37
37
AUX2-R 4.0V
38
38
AUX2-L
4.0V
- 11 -
CXA2074Q/S
Pin No.
QFP SDIP
Symbol
Pin voltage
Equivalent circuit
VCC 3k
Description
39
39
LPOUT-R 4.0V
LPOUT right channel output pin.
147 39 40
580 580
40
40
LPOUT-L 4.0V
LPOUT left channel output pin.
VCC
41
41
LPIN-R
4.0V
10k 147 41 42 47k
Right channel loop input pin.
42
42
LPIN-L
4.0V
4V
Left channel loop input pin.
7 10 20 29 34 43
-- -- -- -- -- --
NC NC NC NC NC NC
-- -- -- -- -- --
(7) (10) (20) (29) (34) (43)
- 12 -
Electrical Characteristics COMPIN input level (100% modulation level) The pin numbers in parenthesis are for the CXA2074Q. (Ta = 25C, VCC = 9V)
Measurement conditions Filter Min. 30 39/40 20 log ('5k'/'1k') 39/40 39/40 15kLPF 39/40 39/40 39/40 23 (21) 20 log ('12k'/'1k') 15kLPF 15kLPF 20 log ('100%'/'0%') 20 log ('NRSW = 0'/ 'NRSW = 1') 0dB = 49mVrms 0dB = 49mVrms
Change PILOT (fH) Level
Main (L + R) (Pre-Emphasis: OFF) = 245mVrms SUB (L - R) (dbx-TV: OFF) = 490mVrms Pilot = 49mVrms SAP Carrier = 147mVrms fH = 15.734kHz
Mode Input pin Typ. 40 490 0 -1.0 0.1 - - 61 150 23 (21) 23 (21) 23 (21) 15kLPF 1kBPF fH BPF 23 (21) 40 23 (21)
PILOT (fH) 0dB
No. Input signal Max. 50 540 1.0 1.0 0.5 0.15 69 190 -3.0 - - 56 60 - -9.0 20 log (`on level'/'off level') BUS RETURN 3.5 -0.5 0.1 0.2 64 70 -35 -6.0 6.0 0.5 - 230 1.0 1.0 2.0 - - -27 -3.0 8.5
No signal Mono 1kHz 100% mod. Pre-em. ON
Item 17 (14) MONO MONO MONO MONO MONO MONO ST ST ST ST ST SAP ST 17 (14) 17 (14) 17 (14)
SUB (L-R), 1kHz, 100% mod., NR ON, SAP Carrier (5fH) SUB (L-R) 1kHz, NR OFF
Signal
Output pin
Unit mA mVrms dB dB % % dB mVrms dB % % dB dB dB dB dB
1 17 (14) 440 -1.2 -3.0 17 (14) 17 (14) 17 (14) 17 (14) 15kLPF 20 log ('100%'/'0%') 15kLPF 17 (14) 17 (14) 17 (14) 17 (14) 17 (14)
SUB (L-R), 1kHz, 200% mod., NR OFF SUB (L-R) 1kHz, 100% mod., NR OFF SUB (L-R) 12kHz, 30% mod., NR OFF SUB (L-R), 1kHz, 100% mod., NR OFF Mono 1kHz, Pre-em. ON Mono 1kHz 200% mod. Pre-em. OFF Mono 1kHz 100% mod. Pre-em. ON Mono 12kHz 30% mod. 20 log Pre-em. ON ('12k'/'1k') Mono 5kHz 30% mod. Pre-em. ON
Current consumption
Icc
2
Main output level
Vmain
3
Main de-emphasis frequency characteristic
FCdeem
4
Main LPF frequency characteristic
FCmain
5
Main distortion
THDm
6
Main overload distortion
THDmmax
- 13 -
ST 17 (14)
7
Main S/N
SNmain
8
Sub output level
Vsub
9
Sub LPF frequency characteristic
FCsub
10
Sub distortion
THDsub
11
Sub overload distortion
THDsmax
12
Sub S/N
SNsub
13
ST SAP Crosstalk
CTst
14
Sub pilot leak
PCsub
CXA2074Q/S
15
Stereo ON level
THst
16
Stereo ON/OFF hysteresis
HYst
No. SAP SAP -3.0 2.5 6.0 - - -6.5 4.0 35 23 23 23 39/40 39/40 23 -0.5 - 1kBPF 39/40 - 0dB = 490mVrms 0dB = 490mVrms 0dB = 490mVrms EXT INT 0dB=490mVrms INT EXT MONO 1kHz 100%, Pre-em. on Sine wave 1kHz, 490mVrms 35/36 37/38 20 log (M2 = "0"/M2 = "1") 1kBPF 1kBPF 1kBPF 7/8 (2/3) 7/8 (2/3) 7/8 (2/3) - - - -75 -90 -90 -60 -80 -75 dB dB dB -90 -75 dB 35 35 35 0 -85 6.0 - - - 39/40 - 0.5 -70 - 2.5 55 70 -9.0 46 60 -12.0 2.0 15kLPF 39/40 39/40 15kLPF 15kLPF 15kLPF 0dB = 490mVrms 0 SAP SAP 15kLPF 1kBPF 40 ST 0dB = 147mVrms BUS RETURN 20 log (`on level'/'off level') SAP 1kHz 100% mod. 20 log ('NRSW NR ON, Pilot (fH) = 1'/'NRSW = 0') 20 log SAP 1kHz, NR OFF ('100%'/'0%') 26 (24) 17 (14) SAP 1kHz 100% mod. NR OFF 15kLPF dB % dB dB dB dB dB dB dB dB dB dB 150 230 mVrms 190
Item
Symbol
Mode
Input pin Input signal Filter Unit Min. Max. Typ.
Measurement conditions
17
SAP output level
Vsap
Output pin 26 (24)
18
SAP LPF frequency characteristic
FCsap
17 (14) 17 (14) SAP 1kHz 100% mod. NR OFF SAP 10kHz, 30% mod. 20 log NR OFF ('10k'/'1k') 26 (24) 26 (24)
19
SAP distortion
THDsap
20
SAP S/N
SNsap
21
SAP ST Cross talk
CTsap
17 (14) 17 (14)
22 SAP 17 (14) Change SAP Carrier (5fH) Level ST-L 300Hz 30% mod. NR ON
SAP ON level
THsap
23 ST ST ST ST EXT INT EXT INT EXT INT EXT EXT 35/36 37/38 Sine wave 1kHz, 490mVrms Sine wave 1kHz, 490mVrms 17 (14) MONO 1kHz 100%, Pre-em. on 35/36 37/38 Sine wave 1kHz, 490mVrms MONO 1kHz, 100%, 20 log (M1 = Pre-em. on "0"/M1 = "1") 20 log (M1 = "0"/M1 = "1") 17 (14) ST-R 3kHz 30% mod. NR ON Sine wave 1kHz, 490mVrms 17 (14)
SAP ON/OFF hysteresis
HYsap
24
ST separation 1 L R
STLsep1
25
ST separation 1 R L
STRsep1
- 14 -
35/36 37/38 17 (14) 35/36 37/38 17 (14)
26
ST separation 2 L R
STLsep2
17 (14) 17 (14) ST-R 300Hz 30% mod. NR ON ST-L 3kHz 30% mod. NR ON
27
ST separation 2 R L
STRsep2
28
LPOUT output level
Vtp
29
30
LPOUT muted amount
MUlp1
MUlp2
31
LSOUT output level
Vls
7/8 (2/3)
-0.9
0
0.9
dB
32
LSOUT cross talk
CTls
CXA2074Q/S
33
LSOUT muted amount
MUls
No. Input signal
Item Input pin
Symbol
Mode
Measurement conditions Filter Min. Typ. Unit Max.
Output pin
34 No signal
LSOUT DC offset
OSls
INT EXT -- -25 0 25 mV
Mute (M2 = 0)/ DC difference when there is no signal 7/8 (2/3) 15kLPF 7/8 (2/3) - 0.01 0.5 7/8 (2/3) 75 88 7/8 (2/3) - 11 -13 11 -13 1kBPF - 7/8 (2/3) 7/8 (2/3) 7/8 (2/3) 7/8 (2/3) 7/8 (2/3) 0.1 12 -12 12 -12 -90 - %
35
LSOUT distortion
THDls
EXT
35/36 37/38 Sine wave 1kHz, 490mVrms Sine wave 1kHz, 490mVrms 15kLPF Sine wave 1kHz, 2Vrms 15kLPF BASS = "F" 0dB = 245mVrms BASS = "0" 0dB = 245mVrms TREBLE = "F" 0dB = 245mVrms TREBLE = "0" 0dB = 245mVrms VOL-L = "0", VOL-R = "0" 0dB = 490mVrms Sine wave 100Hz, 245mVrms Sine wave 100Hz, 245mVrms Sine wave 10kHz, 245mVrms Sine wave 10kHz, 245mVrms Sine wave 1kHz, 490mVrms 20 log ('490mVrms'/ 'No signal') 35/36 37/38 35/36 37/38 35/36 37/38 35/36 37/38 35/36 37/38 35/36 37/38 35/36 37/38
36
LSOUT S/N
SNls
EXT
dB
37 EXT EXT EXT EXT EXT EXT
LSOUT overload distortion
THDlsmax
1.0 13 -11 13 -11 -75
% dB dB dB dB dB
38
BASS maximum value
TBmax
39
BASS minimum value
TBmin
- 15 -
40
TREBLE maximum value
TTmax
41
TREBLE minimum value
TTmin
42
Volume minimum value
VOLmin
CXA2074Q/S
CXA2074Q/S
I2C BUS block items (SDA, SCL) No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 High level input voltage Low level input voltage High level input current Low level input current Low level output voltage SDA (Pin 9) during 3mA inflow Maximum inflow current Input capacitance Maximum clock frequency Minimum waiting time for data change Minimum waiting time for start of data transfer Low level clock pulse width High level clock pulse width Minimum waiting time for start preparation Minimum data hold time Minimum data preparation time Rise time Fall time Minimum waiting time for stop preparation Item Symbol VIH VIL IIH IIL VOL IOL CI fSCL tBUF tHD: STA tLOW tHIGH tSU: STA tHD: DAT tSU: DAT tR tF tSU: STO Min. 3.0 0 -- -- 0 3 -- 0 4.7 4.0 4.7 4.0 4.7 0 250 -- -- 4.7 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 5.0 1.5 10 10 0.4 -- 10 100 -- -- -- -- -- -- -- 1 300 -- ns s ns s s V A V mA pF kHz Unit
I2C BUS load conditions: Pull-up resistor 4k (Connect to +5V) Load capacity 200pF (Connect to GND)
I2C BUS Control Signal
SDA tBUF SCL P S tHD: STA tLOW tHD: DAT tHIGH tSU: DAT Sr tSU: STA tSU: STO P tR tF tHD: STA
- 16 -
CXA2074Q/S
Electrical Characteristics Measurement Circuit CXA2074Q
S6 S5 S4 S3 S2 S1
BUFF FILTERS 15kHz LPF fH BPF 1kHz BPF MEASURES
SIGNAL SIGNAL GENE- GENERATOR RATOR V2 AC V4 AC
SIGNAL SIGNAL GENE- GENERATOR RATOR V5 AC V6 AC R1 3.9k C13 1 35 34 33
TANTALUM
TANTALUM
C10 4.7 36
C12 4.7
C14 10 32
C15 4.7 31 30 29
C17 3.3 28
R4 R6 3k 3.3k C18 C19 0.047 2700p 27 26 25
VCAIN
VETC
NC
AUX1-R
VCATC
NC
VCAWGT
VEWGT
AUX1-L
VEOUT
VE
C2 4.7
37
SAPIN
C28 4.7 24
AUX2-R 38 AUX2-L
SAPOUT
C3 4.7 C4 4.7 SIGNAL GENERATOR C5 4.7 C6 4.7 V3 AC C7 4.7
NOISETC 23 C22 4.7
39
LPOUT-R
STIN 22
40 LPOUT-L
SUBOUT 21
C29 4.7
41 LPIN-R
NC 20
V1 AC
42 LPIN-L
VCC 19 C23 100 VCC V8 9V GND
SIGNAL GENERATOR
43 NC
SAPTC 18 C24 4.7
44 BASSR1 C8 47n
GND 17
GND 45 BASSR2 IREF 16 R8 62k METAL 1%
46 BASSL1 C9 47n
VGR 15 C25 10 SIGNAL GENERATOR V7 AC GND
47 BASSL2
COMPIN 14
LSOUT-R
LSOUT-L
MAINOUT
PCINT1
PCINT2
MAININ
C26 4.7 PLINT 13 C27 1 R7 1MEG
TREL
SDA
C1 6.8n C11 6.8n
SCL
DGND
48 TRER
1
2
3 R2 220
4 R3 220
5
6
NC
7
8 C16 4.7
9
NC
10
11
12
C20 5600P
I2C BUS DATA DGND
R5 C21 100k 0.012
- 17 -
CXA2074S
BUFF FILTER S MEASURE S
SIGNAL GENERATOR
SIGNAL GENERATOR
SIGNAL SIGNAL GENERATOR GENERATOR SIGNAL GENERATOR
V1 AC R2 3.9k R5 3k C21 0.047 C23 2700p 27 26 25 29 28 C25 4.7 C28 4.7 R7 3.3k C15 1 34 31 33 30 32 C17 4.7 AC AC
V2
SIGNAL GENERATOR
V3
V4
V5
V6
S 6 S 5 S 4 S 3 S 2 S 1 15kHz LPF fH BPF 1kHz BPF
AC
AC
AC
C16 10 TANTALUM
42
41
40 36
39
38
37
35
C19 3.3 TANTALUM
C1 4.7
C3 4.7
C4 4.7
C6 4.7
C8 4.7
C10 4.7
C12 4.7
C14 4.7
C29 4.7 24 23 22
C31 100
VE
VCAIN
VETC
LPIN-L
LPIN-R
VCATC
AUX2-L
AUX1-L
AUX2-R
AUX1-R
VEOUT
SAPIN
STIN
VCC
VCC V8 9V GND
VEWGT
LPOUT-L
SAPOUT
LPOUT-R
VCAWGT
BASSR1
BASSR2
BASSL1
BASSL2
TRER
TREL
LSOUT-R
LSOUT-L
SDA
SCL
DGND
MAININ
NOISETC
SUBOUT
1 7 11 8 10 14
2
3
4
5 12
6 9
13
MAINOUT
PCINT1
PCINT2
PLINT
COMPIN
VGR
15 R6 1MEG
16 C24 1
17 C26 4.7
18 C27 10
IREF
19
GND
20
R4 C22 100k 0.012
R8 62k METAL 1%
C2 47n
C5 47n
C7 6.8n R1 220 R3 220 C18 4.7
C9 6.8n
C11 4.7
C13 4.7
C20 5600p
SAPTC
21 C30 4.7 SIGNAL GENERATO R V7 GND AC GND
- 18 -
I2C BUS DATA DGND
CXA2074Q/S
CXA2074Q/S
I2C BUS Register Data Standard Setting Values Register ATT VCO FILTER SPECTRAL WIDEBAND TEST-DA TEST1 FST VOL-L VOL-R BASS TREBLE NRSW FOMO TVSW EXT FEXT1 FEXT2 PSW M1 M2 ATTSW SAPC Number Classifi- Standard of bits cation setting 4 6 6 6 6 1 1 1 6 6 4 4 1 1 1 1 1 1 1 1 1 1 1 A A A A A T T T U U U U U U U U U U U U U S S 9 1F 1F 1F 1F 0 0 0 3F 3F 8 8 -- -- 0 0 0 0 0 1 1 -- -- Fixed by the set specifications External input 1 forced MONO External input 2 forced MONO TVSW output selection Mute OFF Standard setting value Standard setting value Standard setting value TV decoder output selection Standard setting value Normal mode Normal mode 3F = 0dB 3F = 0dB 7 or 8 = 0dB 7 or 8 = 0dB According to the mode control table Standard setting value FST = 0 Center point Adjustment point Contents Setting value when electrical characteristics are measured
Classification A: Adjustment U: User control S: Proper to set T: Test
- 19 -
List of Adjustment Contents Input signal data Measurement Adjustment contents Test mode setting 100Hz 245mVrms None TEST-DA = 1 LPOUT-R output frequency Adjust as close to 62.936kHz as possible Adjust to the center of the FILADJ = 1 condition TEST1 = 1 STA5 (FILADJ) LPOUT-L output level Adjust as close to 490mVrms as possible
The pin numbers in parenthesis are for the CXA2074Q.
Adjustment item
Adjustment data
Input pin
1
MAIN VCA
ATT
COMPIN Pin 17 (Pin 14)
2
ST & SAP VCO 9.4kHz 600mVrms
VCO
None
3
ST & SAP & dbx FILTER
FILTER
COMPIN Pin 17 (Pin 14) ST-L 30% 300Hz Minimize the output level LPOUT-R output level
Low frequency ST separation
WIDEBAND
4 ST-L 30% 3kHz Minimize the output level LPOUT-R output level
COMPIN Pin 17 (Pin 14)
High frequency ST separation
SPECTRAL
COMPIN Pin 17 (Pin 14)
- 20 -
CXA2074Q/S
CXA2074Q/S
Adjustment Method 1. ATT adjustment 1) TEST BIT is set to "TEST1 = 0" and "TEST-DA = 0". 2) Input a 100Hz, 245mVrms sine wave signal to COMPIN and monitor the LPOUT-L output level. Then, adjust the "ATT" data for ATT adjustment so that the LPOUT-L output goes to the standard value. 3) Adjustment range: 30% Adjustment bits: 4 bits 2. Stereo, SAPVCO adjustment 1) TEST BIT is set to "TEST1 = 0" and "TEST-DA = 1". 2) Monitor the LPOUT-R output (4fH free running) frequency in a no input state, and adjust "VCO" adjustment data so that this frequency is as close to 4fH (62.936kHz) as possible. 3) Adjustment range: 20% Adjustment bits: 6 bits 3. Stereo, SAP block, dbx filter adjustment 1) TEST BIT is set to "TEST1 = 1" and "TEST-DA = 0". 2) Input a 9.4kHz, 600mVrms sine wave signal to COMPIN. While monitoring the STATUS FLAG (STA5) condition, adjust the "FILTER" adjustment data. 3) Adjustment range: 20% Adjustment bits: 6 bits Align "FILTER" with the center of the STA5 = 1 (adjustment OK) condition range.
Adjustment point Control data "FILTER"
0 1 0
3F
Measurement data STA5 "FILADJ"
4.Separation adjustment 1) TEST BIT is set to "TEST1 = 0" and "TEST-DA = 0". 2) Set the unit to stereo mode and input the left channel only signal (modulation factor 30%, frequency 300Hz NR-ON) to COMPIN. At this time, adjust the "WIDEBAND" adjustment data to reduce LPOUT-R output to the minimum. 3) Next, set the frequency only of the input signal to 3kHz and adjust the "SPECTRAL" adjustment data to reduce LPOUT-R output to the minimum. 4) The adjustments in 2 and 3 above are performed to optimize the separation. 5) "WIDEBAND" "SPECTRAL" Adjustment range: 30% Adjustment range: 15% Adjustment bits: 6 bits Adjustment bits: 6 bits
- 21 -
CXA2074Q/S
Description of Operation [The pin numbers in parenthesis are for the CXA2074Q.] The US audio multiplexing system possesses the base band spectrum shown in Fig. 1.
PEAK DEV kHz 50 AM-DSB-SC 50
25
25
L-R dbx-TV NR
PILOT
15 SAP dbx-TV NR FM 10kHz 50 - 10kHz 2fH 3fH 4fH 5fH TELEMETRY FM 3kHz 3 6fH 6.5fH f
L+R 5 50 - 15kHz fH
fH = 15.734kHz
Fig. 1. Base band spectrum
I2C BUS DECODER MODE CONTROL (MAIN OUT) (MAIN IN) 4.7
PLL (VCO 8fH) STEREO LPF MVCA
2fHL0 fHL90 fHL0
PILOT DET
(COMPIN)
MAIN LPF DE.EM PILOT CANCEL SUB LPF L-R (DSB) DET
17 (14)
13 (9)
WIDEBAND SUBVCA L+R (SUBOUT) (ST IN)
12 (8)
MATRIX (Lch) NR SW to TVSW
23 24 (21) 4.7 (22)
L-R
SAP BPF
SAP(FM) DET INJ. LOCK
A
SAP LPF
(SAP OUT)
dbx-TV BLOCK
B
(Rch)
26 (24)
NOISE DET
(SAP IN)
I2C BUS DECODER 4.7
27 (25)
MODE CONTROL
SAP DET
I2C BUS DECODER MODE CONTROL
Fig. 2. Overall block diagram (See Fig. 3 for the dbx-TV block)
(ST IN) FIXED VARIABLE DEEMPHASIS DEEMPHASIS
(22) 24
(SAP IN)
NR SW
A
(VE OUT) (VCA IN)
B
VCA to MATRIX
(25) 27
HPF LPF LPF
32 31 (30) 4.7 (31)
RMS DET
RMS DET
Fig 3. dbx-TV block - 22 -
CXA2074Q/S
(AUX2-L) (AUX2-R)
(LPIN-L) (LPIN-R)
38
37 40 39
42
(LPOUT-L) (LPOUT-R)
41
(AUX1-L)
VOL-L
BASS
TREBLE
(LSOUT-L)
36 35
(AUX1-R)
TVSW
PASSSW VOL-R
8 (3) 7 (2)
(LSOUT-R)
(Lch)
(Rch)
from MATRIX
Fig. 4. Sound processor block (1) L + R (MAIN) After the audio multiplexing signal input from COMPIN (Pin 17 (Pin 14)) passes through MVCA, the SAP signal and telemetry signal are suppressed by STEREO LPF. Next, the pilot signals are canceled. Finally, the L - R signal and SAP signal are removed by MAIN LPF, and frequency characteristics are flattened (de-emphasized) and input to the matrix. (2) L - R (SUB) The L - R signal follows the same course as L + R before the pilot signal is canceled. L - R has no carrier signal, as it is a suppressed-carrier double-sideband amplitude modulated signal (DSB-AM modulated). For this reason, the pilot signal is used to regenerate the carrier signal (quasi-sine wave) to be used for the demodulation of the L - R signal. In the last stage, the residual high frequency components are removed by SUB LPF and the L - R signal is input to the dbx-TV block via the NRSW circuit after passing through SUBVCA. (3) SAP SAP is an FM signal using 5fH as a carrier as shown in the Fig. 1. First, the SAP signal only is extracted using SAP BPF. Then, this is subjected to FM detection. Finally, residual high frequency components are removed and frequency characteristics flattened using SAP LPF, and the SAP signal is input to the dbx-TV block via the NRSW circuit. When there is no SAP signal, the Pin 26 output is soft muted. (4) Mode discrimination Stereo discrimination is performed by detecting the pilot signal amplitude. SAP discrimination is performed by detecting the 5fH carrier amplitude. NOISE discrimination is performed by detecting the noise near 25kHz after FM detection of SAP signal. (5) dbx-TV block Either the L - R signal or SAP signal input respectively from ST IN (Pin 24 (Pin 22)) or SAP IN (Pin 27 (Pin 25)) is selected by the mode control and input to the dbx-TV block. The input signal then passes through the fixed de-emphasis circuit and is applied to the variable deemphasis circuit. The signal output from the variable de-emphasis circuit passes through an external capacitor and is applied to VCA (voltage control amplifier). Finally, the VCA output is converted from a current to a voltage using an operational amplifier and then input to the matrix.
- 23 -
CXA2074Q/S
The variable de-emphasis circuit transmittance and VCA gain are respectively controlled by Each of effective value detection circuits. Each of the effective value detection circuits passes the input signal through a predetermined filter for weighting before the effective value of the weighted signal is detected to provide the control signal. (6) Matrix, TVSW, PASSSW The signals (L + R, L - R, SAP) input to "MATRIX" become the outputs for the ST-L, ST-R, MONO and SAP signals according to the BUS data and whether there is ST / SAP discrimination. "TVSW" switches the "MATRIX" output signal, external input signal (input to AUX1-L, R), external input signal (input to AUX2-L, R) and external forced MONO. "PASSSW" switches the "TVSW" output signal and external input signal (input to LPIN-L, R). (7) Sound processor block The sound processor block contains, "BASS/TREBLE" tone control functions, and "VOLUME". BASS: 12dB (1.7dB/STEP at 100Hz) TREBLE: 12dB (1.7dB/STEP at 10kHz) VOLUME: 0 to -80dB (-1.25dB/STEP) (8) Others "MVCA" is a VCA which adjusts the input signal level to the standard level of this IC. "Bias" supplies the reference voltage and reference current to the other blocks. The current flowing to the resistor connecting IREF (Pin 19 (Pin 16)) with GND become the reference current.
Standard input and output levels Input pin COMPIN AUX1-L/AUX1-R AUX2-L/AUX2-R LPIN-L/LPIN-R 1 2 3 Pin No. 17 (14) 36/35 38/37 42/41 Input level 245mVrms1 490mVrms 490mVrms 490mVrms LPOUT output level 490mVrms2 490mVrms 490mVrms -- LSOUT output level3 490mVrms2 490mVrms 490mVrms 490mVrms
MONO, 25kHz Deviation, Pre-Em. off MONO, 25kHz Deviation, Pre-Em. on VOLUME MAX, BASS & TREBLE CENTER
- 24 -
CXA2074Q/S
Register Specifications Slave address SLAVE RECEIVER SLAVE TRANSMITTER 80H (1000 0000) Register table SUB ADDRESS MSB LSB BIT7 ATTSW PSW FST FEXT1 BIT6 BIT5 TEST-DA 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 DATA BIT4 TEST1 VCO (6) FILTER (6) SPECTRAL (6) WIDEBAND (6) NRSW FEXT2 FOMO TVSW SAPC EXT M1 M2 BIT3 BIT2 BIT1 BIT0 81H (1000 0001)
ATT (4)
VOL-L (6) VOL-R (6) BASS (4) TREBLE (4) : Don't Care
Status Registers when TEST1 = 0 STA1 BIT7 STA2 BIT6 STA3 BIT5 SAP STA4 BIT4 NOISE STA5 BIT3 -- STA6 BIT2 -- STA7 BIT1 -- STA8 BIT0 --
POWER STEREO ON RESET when TEST1 = 1 STA1 BIT7 STA2 BIT6
STA3 BIT5 SAP
STA4 BIT4 NOISE
STA5 BIT3 FILADJ
STA6 BIT2 --
STA7 BIT1 --
STA8 BIT0 --
POWER STEREO ON RESET
- 25 -
CXA2074Q/S
Description of Registers Control registers Register ATT VCO FILTER SPECTRAL WIDEBAND TEST-DA TEST1 FST VOL-L VOL-R BASS TREBLE NRSW FOMO TVSW EXT FEXT1 FEXT2 PSW M1 M2 ATTSW SAPC Number of bits Classification1 4 6 6 6 6 1 1 1 6 6 4 4 1 1 1 1 1 1 1 1 1 1 1 A A A A A T T T U U U U U U U U U U U U U S S Input level adjustment STEREO VCO & SAP VCO free running frequency adjustment STEREO and SAP and dbx filter adjustment Adjustment of stereo separation (3kHz) Adjustment of stereo separation (300Hz) Turn to DAC test mode and VCO adjustment mode by means of TEST-DA = 1. Turn to test mode by means of TEST = 1. (Adjustment of FILTER) Turn to forced stereo by means of FST = 1. LSOUT-L output signal level control LSOUT-R output signal level control LSOUT output bass control LSOUT output treble control Selection of the output signal (Stereo mode, SAP mode) Turn to forced MONO by means of FOMO = 1. (Left channel only is MONO during SAP output.) Selection of TV mode or external input mode for LPOUT output Selection of external input 1 mode or external input 2 mode for LPOUT output. (TVSW = 1) External input 1 forced MONO (1: forced MONO ON) External input 2 forced MONO (1: forced MONO ON) Selection of internal mode or LPIN mode for LSOUT output. Selection of LPOUT mute ON/OFF (0: mute ON, 1: mute OFF) Selection of LSOUT mute ON/OFF (0: mute ON, 1: mute OFF) Turn the input stage MVCA off when ATTSW = 1. Selection of SAP mode or L + R mode according to the presence of SAP broadcasting Contents
1 Classification U: User control A: Adjustment S: Proper to set T: Test
- 26 -
CXA2074Q/S
Status registers Register PONRES STEREO SAP NOISE FILADJ Number of bits 1 1 1 1 1 POWER ON RESET detection; Stereo discrimination of the COMPIN input signal; SAP discrimination of the COMPIN input signal; Noise level discrimination of the SAP signal; Status of FILTER adjustment; Contents 1: RESET 1: Stereo 1: SAP 1: Noise 1: OK range
Description of Control Registers ATT (4): Adjust the signal level input to COMPIN (Pin 17 (Pin 14)) to the standard input level (245mVrms). Variable range of the input signal: 245mVrms -5.0dB to +3.0dB 0 = Level min. F = Level max. Adjust STEREO & SAP VCO free running frequency (fo). Variable range: fo 20% 0 = Free running frequency min. 3F = Free running frequency max.
VCO (6):
FILTER (6):
Adjust the filter fo of the ST, SAP and dbx blocks. Variable range: fo 20% 0 = Frequency min. 3F= Frequency max.
SPECTRAL (6): Perform high frequency (fs = 3kHz) separation adjustment. 0 = Level max. 3F = Level min. WIDEBAND (6): Perform low frequency (fs = 300Hz) separation adjustment. 0 = Level min. 3F = Level max. TEST-DA (1): Set DAC output test mode and VCO adjustment mode. 0 = Normal mode 1 = DAC output test mode and VCO adjustment mode In addition, the following outputs are present at Pins 40 and 39. LPOUT-L (Pin 40): DA control DC level LPOUT-R (Pin 39): STEREO VCO oscillation frequency (4fH)
- 27 -
CXA2074Q/S
TEST1 (1):
Set filter adjustment mode. 0 = Normal mode 1 = FILTER (STA5) adjustment mode In addition, the following outputs are present at Pins 40 and 39. LPOUT-L (Pin 40): SAP BPF OUT LPOUT-R (Pin 39): NR BPF OUT Select forced STEREO mode 0 = Normal mode 1 = Forced stereo mode LSOUT-L output signal level control 0 = Volume Min. (-80dB) 3F= Volume Max. (0dB) -1.25 dB/STEP LSOUT-R output signal level control 0 = Volume Min. (-80dB) 3F= Volume Max. (0dB) -1.25 dB/STEP LSOUT output bass control 0 = Bass Min. 7 & 8 = Bass Center (0dB) F = Bass Max.
FST (1):
VOL-L (6):
VOL-R (6):
BASS (4):
TREBLE (4): LSOUT output treble control 0 = Treble Min. 7 & 8 = Treble Center (0dB) F = Treble Max. NRSW (1): Select stereo mode or SAP mode 0 = Stereo mode 1 = SAP mode Select forced MONO mode 0 = Normal mode 1 = Forced MONO mode Select TV mode or external input mode for LPOUT output. 0 = TV mode 1 = External input mode Select external input [1] mode or external input [2] mode for LPOUT output. (TVSW = 1) 0 = External input [1] mode 1 = External input [2] mode
FOMO (1):
TVSW (1):
EXT (1):
- 28 -
CXA2074Q/S
FEXT1 (1):
Turn external input [1] to forced MONO. 0 = Normal mode 1 = External input [1] is forced MONO. Input the same signal to both AUX1-L and AUX1-R. Turn external input [2] to forced MONO 0 = Normal mode 1 = External input [2] is forced MONO Input the same signal to both AUX2-L and AUX2-R. Select INT mode or LPIN mode for LSOUT output. 0 = INT mode 1 = LPIN mode Mute the LPOUT-L and LPOUT-R output. 0 = Mute ON 1 = Mute OFF Mute the LSOUT-L and LSOUT-R output. 0 = Mute ON 1 = Mute OFF Select BYPASS SW of MVCA 0 = Normal mode 1 = MVCA is passed Select the SAP signal output mode When there is no SAP signal, the conditions for selecting SAP output are selected by SAPC. 0 = L + R output is selected 1 = SAP output is selected
FEXT2 (1):
PSW (1)
M1 (1):
M2 (1):
ATTSW (1)
SAPC (1):
- 29 -
CXA2074Q/S
Description of Mode Control Priority ranking: M1/M2 > TVSW/EXT > TEST-DA > TEST1 > (NRSW & FOMO & SAPC) Mode control SAPC = 0 "Select dbx input and TV decoder output" Conditions: FOMO = 0 NRSW = 0 (MONO or ST output) * During ST input: left channel: L, right channel: R * During other input: left channel: L + R, right channel: L + R NRSW = 1 (SAP output) * When there is "SAP" during SAP discrimination - left channel: SAP, right channel: SAP * When there is "No SAP", output is the same as when NRSW = 0. SAPC = 1 "Select dbx input and TV decoder output" Conditions: FOMO = 0 NRSW = 0 (MONO or ST output) As on the left
NRSW
NRSW = 1 (SAP output) * Regardless of the presence of SAP discrimination, dbx input: "SAP" left channel: SAP, right channel: SAP However, when there is no SAP, SAPOUT output is soft muted (-7dB)
"Forced MONO" FOMO FOMO = 1 * During SAP output: left channel: L + R, right channel: SAP * During ST or MONO output: left channel: L + R, right channel: L + R Change the selection conditions for "MONO or ST output" and "SAP output". SAPC = 0: Switch to SAP output when there is SAP discrimination. Do not switch to SAP output when there is no SAP discrimination. SAPC = 1: Switch to SAP output regardless of whether there is SAP discrimination. "MUTE" M1/M2 M1 = 0: LPOUT output is muted. M2 = 0: LSOUT output is muted. "TV mode/external input mode selection" TVSW = 0: Set LPOUT output to TV mode. TVSW = 1: Set LPOUT output to external input mode. EXT = 0: Set LPOUT output to external input [1] mode. (TVSW = 1) EXT = 1: Set LPOUT output to external input [2] mode. (TVSW = 1) "TEST1" TEST1 = 1 Return adjustment data with STATUS REGISTER as an adjustment mode. In addition, outputs are as follows. left channel: SAP BPF OUT right channel: NR BPF OUT "TEST-DA" TEST-DA = 1 Used to adjust the D/A TEST and VCO. left channel: D/A output right channel: STVCO oscillation frequency (4fH)
SAPC
TVSW/EXT
TEST1
TEST-DA
- 30 -
CXA2074Q/S
Decoder Output and Mode Control Table 1 (SAPC = 1) Input signal mode ST 0 0 MONO 1 0 0 0 0 1 1 1 STEREO 1 1 1 1 1 1 0 0 MONO & SAP 0 0 0 0 1 1 STEREO & SAP 1 1 1 1 Mode detection SAP 0 0 0 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 NOISE 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Mode control NRSW 0 1 1 0 1 1 0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 1 1 1 1 FOMO 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SAPC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 dbx input MUTE SAP SAP MUTE (SAP) (SAP) L-R MUTE L-R MUTE SAP SAP (SAP) (SAP) MUTE MUTE SAP SAP (SAP) (SAP) L-R MUTE SAP SAP (SAP) (SAP) Output Lch L+R SAP L+R L+R (SAP) L+R L L+R L L+R SAP L+R (SAP) L+R L+R L+R SAP L+R (SAP) L+R L L+R SAP L+R (SAP) L+R Rch L+R SAP SAP L+R (SAP) (SAP) R L+R R L+R SAP SAP (SAP) (SAP) L+R L+R SAP SAP (SAP) (SAP) R L+R SAP SAP (SAP) (SAP)
Note (SAP) : The SAPOUT output signal is soft muted (approximately -7dB). The signal is soft muted when NOISE = 1. : Don't care. 1 SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is inputted in the weak electric field. "NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN.
- 31 -
CXA2074Q/S
Decoder Output and Mode Control Table 2 (SAPC = 0) Input signal mode ST 0 0 MONO 1 0 0 0 1 1 1 STEREO 1 1 1 1 1 1 0 0 0 MONO & SAP 0 0 0 0 0 1 1 1 STEREO & SAP 1 1 1 1 1 Mode detection SAP 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 NOISE 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Mode control NRSW FOMO 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SAPC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dbx input MUTE MUTE MUTE (SAP) (SAP) L-R MUTE L-R MUTE L-R MUTE (SAP) (SAP) MUTE MUTE SAP SAP MUTE MUTE (SAP) (SAP) L-R MUTE SAP SAP L-R MUTE (SAP) (SAP) Output Lch L+R L+R L+R (SAP) L+R L L+R L L+R L L+R (SAP) L+R L+R L+R SAP L+R L+R L+R (SAP) L+R L L+R SAP L+R L L+R (SAP) L+R Rch L+R L+R L+R (SAP) (SAP) R L+R R L+R R L+R (SAP) (SAP) L+R L+R SAP SAP L+R L+R (SAP) (SAP) R L+R SAP SAP R L+R (SAP) (SAP)
Note (SAP) : The SAPOUT output signal is soft muted (approximately -7dB). The signal is soft muted when NOISE = 1. : Don't care. 1 SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is inputted in the weak electric field. "NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN. - 32 -
CXA2074Q/S
Mode Control Table 3 M1 1 2 3 4 5 6 0 1 1 1 1 1 TVSW - 0 1 1 1 1 EXT - - 0 0 1 1 FEXT1 - - 0 1 - - FEXT2 - - - - 0 1 LPOUT-L MUTE TV (L) AUX1-L AUX1-L AUX2-L AUX2-L LPOUT-R MUTE TV (R) AUX1-R AUX1-L AUX2-R AUX2-L
TV (L) / TV (R) are selected in MATRIX TV (L): MONO, ST-L, SAP, (SAPBPFout, D/Aout) TV (R): MONO, ST-R, SAP, (NRBPFout, STVCO freerun (4fH))
I2C BUS Signal There are two I2C signals, SDA (Serial DATA) and SCL (Serial CLOCK) signals. SDA is a bidirectional signal. * Accordingly there are 3 values outputs, H, L and HIZ.
H
L
HIZ
L
* I2C transfer begins with Start Condition and ends with Stop Condition.
Start Condition S Stop Condition P
SDA
SCL
- 33 -
CXA2074Q/S
* I2C data Write (Write from I2C controller to the IC)
L during Write MSB HIZ SDA MSB LSB HIZ
SCL S
1
2
3 Address
4
5
6
7
8
9 ACK
1 Sub Address
8
9 ACK
MSB
LSB HIZ HIZ
1
8
9
1
8
9
DATA (n)
ACK
DATA (n + 1)
ACK
DATA (n + 2)
HIZ
HIZ
8 DATA
9 ACK
1 DATA
8
9 P ACK
Data can be transferred in 8-bit units to be set as required. Sub address is incremented automatically.
* I2C data Read (Read from the IC to I2C controller)
H during Read HIZ SDA
SCL S
1
6
7
8
9
1
7
8
9 P
Address
ACK
DATA
ACK
* Read timing
MSB IC output SDA
LSB
SCL
9
1
2
3
4
5
6
7
8
9
Read timing
ACK
DATA
ACK
Data Read is performed during SCL rise.
- 34 -
CXA2074Q/S
Input level vs. Distortion characteristics 1 (MONO)
Input signal: MONO (Pre-emphasis on), 1kHz 0dB = 100% modulation level VCC = 9V, 30kHz using LPF Measurement point: LPOUT-L/R
Input level vs. Distortion characteristics 2 (Stereo)
Input signal: Stereo L = -R (dbx-TVNR ON), 1kHz 0dB = 100% modulation level VCC = 9V, 30kHz using LPF, ST mode Measurement point: LPOUT-L/R
1.0
10
Distortion [%]
Distortion [%]
0.1 1.0 Standard level (100%) -10 0 Input level [dB] -10 0 Input level [dB] 10 Standard level (100%) 10
Input level vs. Distortion characteristics 3 (SAP)
Input signal: SAP (dbx-TVNR ON) 1kHz, 0dB = 100% modulation level VCC = 9V, 30kHz using LPF, SAP mode Measurement point: LPOUT-L/R
10
Distortion [%]
1.0
Standard level (100%) -10 0 Input level [dB] 10
- 35 -
CXA2074Q/S
Stereo LPF frequency characteristics
10
5
Gain [dB]
0
-5
-10
0
20
40
60
80
100
Frequency [kHz]
Main LPF and Sub LPF frequency characteristics
30
Gain (FC main and FC sub) [dB]
20 10 0 -10 -20 -30 -40 -50 1 2 5 7 10 20 50 70 100 Frequency [kHz]
SAP frequency characteristics and group delay
100 20 5fH 10 Gain 90 80
Gain [dB]
60 0 50 40 -10 Group delay 3.8fH 20 40 60 80 30 20 -20 6.2fH 100 10 0 120
Frequency [kHz]
- 36 -
Group delay [s]
70
CXA2074Q/S
BASS-TREBLE characteristics
BASS. MAX +12
TREBLE. MAX
+8
Boost amount [dB]
+4
0
-4
-8
-12 BASS. MIN 20 100 1k Frequency [Hz] Input: AUX1, 2 245mVrms Output:LSOUT TREBLE. MIN 10k 20k
Volume characteristics
0
-20
LSOUT output level [dB]
-40
-60
-80 Input: AUX1, 2 1kHz, 490mVrms Output:LSOUT -100 0 F 1F 2F 3F Control data VOL-L, VOL-R
- 37 -
CXA2074Q/S
Package Outline CXA2074Q
Unit: mm
48PIN QFP (PLASTIC)
15.3 0.4 + 0.4 12.0 - 0.1 + 0.1 0.15 - 0.05
36
25
0.15
37
24
48
13
+ 0.2 0.1 - 0.1
1 + 0.15 0.3 - 0.1
12
0.8
0.12 M
+ 0.35 2.2 - 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-48P-L04 QFP048-P-1212-B LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER / PALLADIUM PLATING COPPER / 42 ALLOY 0.7g
CXA2074S
42PIN SDIP (PLASTIC) 600mil
+ 0.1 - 0.05
22
42
15.24 0.25
+ 0.3 13.0 - 0.1
0.25
0 to 15 21 0.5 0.1
+ 0.4 37.8 - 0.1
1 1.778 0.25
0.9 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SDIP-42P-02 SDIP042-P-0600-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 4.4g
- 38 -
3.0 MIN
+ 0.4 4.6 - 0.1
0.5 MIN
0.9 0.2
13.5

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